I've got some questions about the Z270 Supercarrier - Quite a few actually but I'll just start off with one and we can take it from there afterwards.

One of the features of the Supercarrier is thunderbolt 3 @ upto 40 Gb/s which will use 8 PCI-e lanes.

Are these lanes taken from the chipset? [I've made the assumption this is so] but I could be wrong.

I made a mistake with an assumption for integrated graphics using CPU PCI-e lanes until somebody corrected me and informed me that no CPU PCI-e lanes were used for IGP.

Z270 chipset allows for up to 24 PCI-e lanes to the chipset whilst the CPU will allow for 16 PCI-e lanes to the CPU.

Below is the diagram for the PCH Intel Flexi I/O

https://content.hwigroup.net/images/editorial/600/007793_intel_z270_x299_flexible_io.jpg

There is also a PLEX chip which makes things more interesting.

Anyway, where do the lanes comes from to use thunderbolt 3 on this Z270 Supercarrier?

In a way I'd be hoping they are away from the PCI-e lanes to the chipset as this would leave more lanes for other things.

Obviously the TH3 lanes have to come from somewhere so it's either of the following

1. Chipset PCI-e lanes

2. PCI-e lanes CPU [but there is only 16 CPU lanes even if there is a PLEX chip.

3. Thunderbolt 3 is integrated into the motherboard and is free of the CPU lanes and chipset lanes.

I'd like option 3 to be the answer for most flexibility.

Now I'm learning more about different platforms and their chipsets etc...... it does give rise to confusion and I'd like to mentally plan how I'd use the system and what would be connected and which resources it would use - Thanks