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  <title>ASRock Forums : z370m pro4 VRM phases</title>
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   <title><![CDATA[z370m pro4 VRM phases : I registered only to answer the...]]></title>
   <link>https://forum.asrock.com/forum_posts.asp?TID=6376&amp;PID=53882&amp;title=z370m-pro4-vrm-phases#53882</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://forum.asrock.com/member_profile.asp?PF=10348">mark5916</a><br /><strong>Subject:</strong> 6376<br /><strong>Posted:</strong> 24 Jul 2018 at 9:39pm<br /><br />I registered only to answer the question of The OP.&nbsp;<div><br></div><div>As you know that this board uses an Intersil&nbsp;<span style=": rgb43, 43, 43;">&nbsp;ISL95856 PWM controller...&nbsp;</span></div><div><span style=": rgb43, 43, 43;"><br></span></div><div><span style=": rgb43, 43, 43;">That PWM controller can do a&nbsp;</span>&nbsp;4-, 3-, 2-, or 1-phase design for the CPU VCC, and a&nbsp;&nbsp;3-, 2-, or 1-phase design for the VCCGT (integrated graphics processor)&nbsp;&nbsp;</div><div><br></div><div>ON that board (as with many other budget boards) ASRock uses a 4+3 phase design.&nbsp;</div><div><br></div><div>ASRock doubles the number of power stage components on the CPU VCore rails to get eight phases.</div><div><br></div><div>But in reality that's a 4 phase (with double the mosfets &#091;most probably&#093; in parallel mode)</div><div><br></div><div>So, two low side and two high side mosfets (removing the mosfets heat sink would help on that matter) and double the inductors.&nbsp;</div><div><br></div><div>The remaining three phases are for the IGP.</div><div><br></div><div>So, as you very well have formulated, that's a 4+3 phase design board! :)&nbsp;&nbsp;</div>]]>
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   <pubDate>Tue, 24 Jul 2018 21:39:45 +0000</pubDate>
   <guid isPermaLink="true">https://forum.asrock.com/forum_posts.asp?TID=6376&amp;PID=53882&amp;title=z370m-pro4-vrm-phases#53882</guid>
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   <title><![CDATA[z370m pro4 VRM phases : I understand why there&amp;#039;s...]]></title>
   <link>https://forum.asrock.com/forum_posts.asp?TID=6376&amp;PID=41125&amp;title=z370m-pro4-vrm-phases#41125</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://forum.asrock.com/member_profile.asp?PF=7779">Maxmiz</a><br /><strong>Subject:</strong> 6376<br /><strong>Posted:</strong> 16 Dec 2017 at 8:19pm<br /><br />I understand why there's so much vdrop. Plus the top ones don't heat up, it looks like they're not even activated.<br>]]>
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   <pubDate>Sat, 16 Dec 2017 20:19:11 +0000</pubDate>
   <guid isPermaLink="true">https://forum.asrock.com/forum_posts.asp?TID=6376&amp;PID=41125&amp;title=z370m-pro4-vrm-phases#41125</guid>
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   <title><![CDATA[z370m pro4 VRM phases : Any answer ? I&amp;#039;m curious...]]></title>
   <link>https://forum.asrock.com/forum_posts.asp?TID=6376&amp;PID=41089&amp;title=z370m-pro4-vrm-phases#41089</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://forum.asrock.com/member_profile.asp?PF=7840">Milan</a><br /><strong>Subject:</strong> 6376<br /><strong>Posted:</strong> 16 Dec 2017 at 3:13am<br /><br /><a href="" target="_blank" rel="nofollow"></a>Any answer ? I'm curious too....]]>
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   <pubDate>Sat, 16 Dec 2017 03:13:08 +0000</pubDate>
   <guid isPermaLink="true">https://forum.asrock.com/forum_posts.asp?TID=6376&amp;PID=41089&amp;title=z370m-pro4-vrm-phases#41089</guid>
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   <title><![CDATA[z370m pro4 VRM phases : Furthermore, why are those top...]]></title>
   <link>https://forum.asrock.com/forum_posts.asp?TID=6376&amp;PID=38209&amp;title=z370m-pro4-vrm-phases#38209</link>
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    <![CDATA[<strong>Author:</strong> <a href="https://forum.asrock.com/member_profile.asp?PF=7092">xpl</a><br /><strong>Subject:</strong> 6376<br /><strong>Posted:</strong> 20 Oct 2017 at 6:13pm<br /><br /><a href="" target="_blank" rel="nofollow"></a>Furthermore, why are those top mosfets not heatsinked? This is especially concerning because the motherboard has been designed to accommodate a heatsink for those fets as there are through-hole mounting points there labeled "MOS_HEATSINK2"<br>]]>
   </description>
   <pubDate>Fri, 20 Oct 2017 18:13:12 +0000</pubDate>
   <guid isPermaLink="true">https://forum.asrock.com/forum_posts.asp?TID=6376&amp;PID=38209&amp;title=z370m-pro4-vrm-phases#38209</guid>
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   <title><![CDATA[z370m pro4 VRM phases : Aloha,The VRM implementation on...]]></title>
   <link>https://forum.asrock.com/forum_posts.asp?TID=6376&amp;PID=38208&amp;title=z370m-pro4-vrm-phases#38208</link>
   <description>
    <![CDATA[<strong>Author:</strong> <a href="https://forum.asrock.com/member_profile.asp?PF=7092">xpl</a><br /><strong>Subject:</strong> 6376<br /><strong>Posted:</strong> 20 Oct 2017 at 5:19pm<br /><br />Aloha,<br><br>The VRM implementation on this board is provided by the <a href="http://www.intersil.com/en/products/power-management/computing-power-vrm-imvp/multiphase-c&#111;ntrollers/ISL95856.html" target="_blank" rel="nofollow">ISL95856 "4+3 Multiphase PWM Regulator"</a><br><br>The marketing statement on the <a href="http://www.asrock.com/mb/Intel/Z370M%20Pro4/index.us.asp" target="_blank" rel="nofollow">ASRock page for the z370m pro4</a> states "10 Power Phase design"<br><br>How, might you wonder, does a 4+3 controller produce 10 distinct phases?<br><br>I wondered, and pulled out my DMM on continuity mode.<br><br>In reality, what appear to be 11 chokes around the z370m pro4 socket, are 6 chokes.<br><br>Ten of the chokes are configured in parallel pairs of two chokes, making a total of five phases plus the one remaining which I assume is for VTT.<br><br>What is more awkward is that the totem-pole mosfets are configured in quads. Paralleled lower-quality SM4336N mosfets act as the upper mosfet of the totem, and two paralleled higher-quality SM4337N mosfets act as the lower mosfet of the totem.<br><br>ASRock, please explain the marketing. I was convinced that this would be 10 distinct power phases. I am not comfortable overclocking on something which is - in reality - 3+2, or 3 phases for the processor, 2 for the iGP.<br><br><img src="https://www.asrock.com/mb/photo/Z370M%20Pro4%28L2%29.png" height="1000" width="1200" border="0" /><br><span style="font-size:10px"><br /><br />Edited by xpl - 21 Oct 2017 at 6:00am</span>]]>
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   <pubDate>Fri, 20 Oct 2017 17:19:00 +0000</pubDate>
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