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Max_payload setting in BIOS

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futurehitech View Drop Down
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    Posted: 11 Jul 2015 at 4:54am
Hi,

In our application, we would need to change the max_payload setting in BIOS for the PCIe bus. I understand that the value can range from 128 to 4096 bytes. we are interested in setting it to 4096 Bytes. However, I do not see such an option in BIOS, but from testing, we notice the MB is taking 256 Byte as the default/max value. 

Could you let me know what is the roadmap on enabling the max_payload for PCIe bus and what is the max number? 

Thanks,

FHT 
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odiebugs View Drop Down
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Post Options Post Options   Thanks (0) Thanks(0)   Quote odiebugs Quote  Post ReplyReply Direct Link To This Post Posted: 11 Jul 2015 at 10:59am
Welcome to the board. Smile

You probably won't see ( TLP ) Max payload,  anymore. Not after the LGA 1366.  That was the day's when there was a north and south bridge. Now with the north on the CPU and a South- chipset,  and much higher lanes, they are more likely set to max default as there is no reason to limit them with what they can transfer now.  Before,   the root port could be flooded with data and cause crashing.

This is my understanding, you could contact support and see if it was possible to add this back in a modded BIOS for you, that's all I can tell you.
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Post Options Post Options   Thanks (1) Thanks(1)   Quote parsec Quote  Post ReplyReply Direct Link To This Post Posted: 11 Jul 2015 at 2:12pm
Originally posted by futurehitech futurehitech wrote:

Hi,

In our application, we would need to change the max_payload setting in BIOS for the PCIe bus. I understand that the value can range from 128 to 4096 bytes. we are interested in setting it to 4096 Bytes. However, I do not see such an option in BIOS, but from testing, we notice the MB is taking 256 Byte as the default/max value. 

Could you let me know what is the roadmap on enabling the max_payload for PCIe bus and what is the max number? 

Thanks,

FHT 

I've never seen an option in a contemporary ASRock board's BIOS/UEFI to set the PCIe payload size. All I can suggest is checking the PCIe 3.0 specification, which discusses various payload sizes and in general where they are set:

http://komposter.com.ua/documents/PCI_Express_Base_Specification_Revision_3.0.pdf
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Post Options Post Options   Thanks (0) Thanks(0)   Quote odiebugs Quote  Post ReplyReply Direct Link To This Post Posted: 11 Jul 2015 at 5:49pm
Pages 546 - 553

Edited by odiebugs - 11 Jul 2015 at 5:51pm
asrocking
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