X370 Gaming K4 BIOS 3.30 9/14/2017

datonyb wrote: ShampooCA wrote: I have a feeling that information is going to go right over many novice users' heads, and the forum is going to flood with "BIOS 3.30 bricked my board, I can't boot with my RAM that could only do 2133MHz!". Since no one bothers to check compatibility before putting stuff together these days. Here we go!  LOL I'm very content with my current setup on BIOS 3.00, so I won't be updating....but then again I say that everytime.   It probably won't help my CPU overclock, but going to try for 4GHz on this one.  I'm currently stable at 3.85GHz. Cheers to frequent BIOS updates!  :) as i understand it 2133 will be fine this bios update was to allow jedec 2666 to work at 2666 stock not get downclocked to 2400 or 2133 at stock setings

datonyb, you are right. This only applies to memory whose stock/JEDEC speed is 2666.

Of course setting 2133 or 2400 JEDEC speed memory automatically to 2666 would not be good, but that is not the point of this update.

This could be considered a bug fix, if JEDEC 2666 speed DDR4 memory was being downclocked automatically. But as the JEDEC/stock speed of DDR4 has evolved from 2133 to 2400, and now 2666 at least with the model of memory listed in the description, it is really an adjustment.

Since Ryzen processors support DDR4 2666 speed memory as a non-OC speed, this makes sense. But there are earlier Intel processors whose non-OC memory speed is 2133 or 2400. So the memory model in the description seems to be designed specifically for use with Ryzen processors. Which is why this is an important update.

This model of memory makes me wonder about my G.SKILL FlareX, whose JEDEC speed is 2400.

Or is this an example of the disconnect between Ryzen processor memory specs, and the products provided by memory manufactures? Memory manufactures generally don't want their products to be very specific to a platform, since they would sell fewer of them due to compatibility.

Yes, as others said, this is a good indicator AMD is still perfecting memory compatibility at IMC side of things.