X370 Killer SLI/ac BIOS Corrections - P-states/XMP
Printed From: ASRock.com
Category: Technical Support
Forum Name: AMD Motherboards
Forum Description: Question about ASRock AMD motherboards
URL: https://forum.asrock.com/forum_posts.asp?TID=5884
Printed Date: 17 May 2024 at 11:09am
Software Version: Web Wiz Forums 12.04 - http://www.webwizforums.com
Topic: X370 Killer SLI/ac BIOS Corrections - P-states/XMP
Posted By: ksosx86
Subject: X370 Killer SLI/ac BIOS Corrections - P-states/XMP
Date Posted: 21 Aug 2017 at 7:09am
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Ever since BIOS ver. "2.20" the following options no longer appear in the latest BIOS "3.10" yet are listed in the latest shipping product manual, please correct this: - CPU OVP - CPU OCP - UVP In addition, when creating custom p-states for under "Advanced" > "AMD CBS" > "Zen Common Options" > "Custom Core Pstates" there is a bug. The bug is this, in Custom Pstate0 - you can't exceed the Pstate0 VID value of "20". Meaning if you were for instance, to enter a value of per say "1a" which is a voltage of 1387500 the system will cap pstates at the lower Pstate in the chain. Meaning "Pstate1" or whichever Pstate has a voltage equal to "1350000" or lower. In short, as of now none of your posted BIOS' on your site for this board allow one to create a Pstate with a voltage exceeding "1.35v" probably because you took out the option to disable CPU OVP, OCP & UVP is my guess but I could be wrong. - Lastly XMP: When an XMP profile is enabled (In regards to the 3.10 BIOS) if one wants to override one value of the XMP profile - such as the CAS Latency or Timing rate from 1T to 2T - you have the option to change their values but the override doesn't take effect as verified by CPU-Z in the operating system. Please correct this. That's my feedback for your 3.10 BIOS - please resolve it in a timely manner as the P-State issue and the OVP - UVP & OCP points in particular are especially frustrating since they're still in the product manual as advertised options! Thanks. Otherwise I'm really enjoying my motherboard. |
Replies:
Posted By: parsec
Date Posted: 21 Aug 2017 at 8:32am
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Questions for you, as I explore your comments. I have the same board and am currently using UEFI version 3.00. Besides the CPU OVP, OVP, and UVP options, do your comments about the VCore being limited to 1.35V apply to every UEFI version since 2.20 as you wrote, or does it ONLY apply to UEFI version 3.10? It seems you said every version since 2.20 has that behavior, but I want to verify that applies to all of your comments. What are you using to monitor VCore? CPU-Z? Another monitoring program? When you try to change the VCore via the PState0 VID, what do you have configured for VCore in the OC Tweaker screen? I am able to set a VCore value greater than 1.350V via setting in OC Tweaker. Changes there are not reflected in PState0, ie the VID does not change from 20. Which screen are you using to change memory timings? ------------- http://valid.x86.fr/48rujh" rel="nofollow"> 
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ksosx86 wrote:Posted By: ksosx86
Date Posted: 21 Aug 2017 at 9:34am
The P-state 1.35v limit I'm running into applies to 3.10 including but not limited to: -2.40 -2.50 -3.00 -3.10 Those are the ones now on the site as of current that I've flashed to my board and tried. I'll try explaining the situation again. Without changing any other options (leaving the board settings on defaults) and only applying clock frequencies & voltages via P-states one cannot exceed the voltage of 1.35volts. which is registered in "PstateX VID" as the Value "20" Meaning if you were to say enter a value greater than 1.35v via P-states (20) such as 1.3875v (1a) the system will not activate whatever frequency you have entered with that corresponding P-state - lets say that frequency is 3.8 GHz or even 3.9 GHz (DID = 8) & (FID = 98) once in the OS that P-state won't activate because the voltage corresponding with that p-state of 3.9 GHz in this case is exceeding 1.35v - that is the bug. Thus - you'll see in task manager, HWmonitor or any monitoring app the system "capping" or "throttling" when under load at say "3GHz" or whatever the "second" injected Pstate is. Now do you understand? UPDATE: Example OS - Windows Pro x64 Creator's Edition ** I can only confirm that the below XMP/Memory issue is specific to 3.10 BIOS & 2.40 BIOS, I haven't tested every other one ** - Memory timing is being changed via "OC Tweaker > DRAM Timing Configuration" If I apply XMP profile and then for instance attempt to change "Command Rate" at the bottom from 1T (applied by XMP) to 2T (Specified by SPD) it allows me to change in UEFI but isn't confirmed by OS (CPU-z / AIDA64) same issue with changing CAS Latency)
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Posted By: parsec
Date Posted: 21 Aug 2017 at 11:21am
My main question was your VCore configuration in OC Tweaker. The rest I understand. Currently the OC Tweaker screen controls VCore, not the FID in a PState. I understand how you want that changed. Also, the core frequency in the OC Tweaker screen is tied to PState0, buy only one way. Changing it on OC Tweaker changes PState0, changing it in PState0 does not change it in OC Tweaker. We also see that with VCore, as you know. I tried the 1a VID in PState0, and confirmed it is then ignored and PState1 is used, as you described. The default behavior seems as if the 1a VID is invalid, making that PState invalid, and then not used. I can't comment on whether or not PState0 has a bug in the VID value, I'm not sure either way, but a quick read in the thread below seems to indicate the behavior you experienced is typical of a Ryzen system and PState0. That is, unless you can show us otherwise, which would be great. Note that this guide states the VCore used by PState0 must be adjusted by using the standard offset voltage configuration settings, in a screen like OC Tweaker: https://hardforum.com/threads/ryzen-pstate-overclocking-method-calculation-and-calculator.1928648/" rel="nofollow - https://hardforum.com/threads/ryzen-pstate-overclocking-method-calculation-and-calculator.1928648/ Another PState OC guide I found did not suggest changing the PState0 VID value from the standard value. That is 20 for the 1800X and 1700X. I also cannot comment on whether or not the change you desire will ever be implemented. At this point, I personally don't know what is correct. I would love to see AMD's guide to PState over clocking... if it can be found. DRAM timings should be adjusted in the Advanced\AMD CBS\DRAM Timing Configuration screen. Command Rate should be adjusted in the Advanced\AMD CBS\UMC Common Options\DDR4 Common Options\DRAM Controller Configuration\Cmd2T screen. ------------- http://valid.x86.fr/48rujh" rel="nofollow">
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Posted By: ksosx86
Date Posted: 21 Aug 2017 at 11:40am
If as you suggested in the above reply, which I thoroughly read and greatly appreciate - I'll need to apply a value of 20 to Pstate0 with a manual Vcore offset and play around a little far as that goes... That will achieve a Pstate0 OC if I understand correctly? Thank you for that. UPDATE: I was able to resolve enabling 2T timing by disabling "Gear Down Mode" under "OC Tweaker\DRAM Timing Configuration" - This in turn allowed me to lower CAS Latency timings as well (the RAM didn't seem to be able to handle that before likely due to 1T) either way - Please disregard that factor of my initial post. EDIT: Aside from the P-states issue you addressed. Can CPU OVP / OCP & UVP be added back into current versions of the BIOS by the development team/ BIOS group. Whomever is responsible for them? Those still are remaining issues out of the hands of troubleshooting etc that need patching. Unless you have a solution I'm unaware of. |