asrock g41c-gs r2.0 ddr2 ram issue

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I have a Q6600 and am trying to use 2x 2GB Corsair TWIN2X4096-6400C5 (CM2X2048-6400C5). This ram is DDR2, 800mhz and DS. Wont boot the BIOS. but will with different set of ddr2 ram at 533mhz. Also the same happens on a duplicate motherboard and ram using a Q9530. So if it is the ram that has gone bad, it would have had to have happened to both sets simultaneously. And both sets were pulled from working systems.

This all would point to a procedure not obvious, as the ram is listed in this QVL http://www.asrock.com/mb/memory/G41C-GS.pdf .  I notice the "R2.0" is missing, but the R2.0 QVL is missing a ddr2 listing. But I doubt there is a compatibility problem.

I have returned everything to the out-of-box settings (w/ CMOS not reset), and ask if anyone knows this procedure, for posterity.

Also the unique opportunity to have on this side of any debug with 2 system this close should aid in uncovering why this, what should be a simple problem, should exist.

Edited by Courine - 01 Aug 2016 at 2:00pm

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Courine Members Profile Send Private Message Find Members Posts Add to Buddy List Newbie Joined: 01 Aug 2016 Status: Offline Points: 11	Post Options Post Reply Quote Courine Report Post Thanks(0) Quote Reply Posted: 01 Aug 2016 at 12:54pm
	I have a Q6600 and am trying to use 2x 2GB Corsair TWIN2X4096-6400C5 (CM2X2048-6400C5). This ram is DDR2, 800mhz and DS. Wont boot the BIOS. but will with different set of ddr2 ram at 533mhz. Also the same happens on a duplicate motherboard and ram using a Q9530. So if it is the ram that has gone bad, it would have had to have happened to both sets simultaneously. And both sets were pulled from working systems. This all would point to a procedure not obvious, as the ram is listed in this QVL http://www.asrock.com/mb/memory/G41C-GS.pdf . I notice the "R2.0" is missing, but the R2.0 QVL is missing a ddr2 listing. But I doubt there is a compatibility problem. I have returned everything to the out-of-box settings (w/ CMOS not reset), and ask if anyone knows this procedure, for posterity. Also the unique opportunity to have on this side of any debug with 2 system this close should aid in uncovering why this, what should be a simple problem, should exist. Edited by Courine - 01 Aug 2016 at 2:00pm