New AGESA 1.0.0.6 |
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Lisanderus
Newbie Joined: 30 Apr 2017 Status: Offline Points: 10 |
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Edited by Lisanderus - 12 Jun 2017 at 2:02pm |
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datonyb
Senior Member Joined: 11 Apr 2017 Location: London U.K. Status: Offline Points: 3139 |
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to be honest i didnt try p1 or p2 as it was set on previos bios but never seemed to kick in (probably due to how i set cool n quiet etc so i didnt bother with agesa 1006 |
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3800X, powercolor reddevil vega64, gskill tridentz3866, taichix370, evga750watt gold |
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noneis
Newbie Joined: 07 Jun 2017 Status: Offline Points: 13 |
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Ryzen is voltage limited at around 0.575-0.6V which rises with temperature. It is also rather hard to test, because instability usually occurs during transition from P0 state to lower one. There are too reasons for this: 1.) At higher temperatures Ryzen needs slightly higher voltage for given clock. So Ryzen stable voltage for lower P-State is highest right after transition from P0 State (or Boost) 2.) During transition to lower P-state voltage drops below set value before vrms react. At low clocks voltage curve is kind of flat all the way to ~2100. From ~2100 to ~3300 Ryzen needs ~25mV for 100Mhz. Necessary voltage above 3.3 Ghz is increasing much faster. Stilt analyzed Ryzen voltage curve from 2 to 4 GHz. https://forums.anandtech.com/threads/ryzen-strictly-technical.2500572/ For example my chip is stable at these clocks and voltages: 1.2Ghz @ 0.625 V @ 80C 1.55 @ 0.650 V @ 80C 2.1 @ 0.725 V @ 80C 2.7 @ 0.875V @ 80C 2.8 @ 0.900 V @ 80C 3.7 @ 1.1875 V @ 80C 2.1 GHz is sweet spot where "flat" voltage curve starts to linearly increase. This clock yields 35% higher performance compared to stock for only 20% lower power efficiency. (considering undervolted stock P2 voltage from ~0.825 V to 0.650 V). CPU doesn't have to use less power efficient P1 state as often providing higher peak performance under low load. It's optimal clock for P2 state because of this and Ryzens fast core parking. This is especially beneficial during highly multithreaded low utilization workloads such as video playback and/or when using power saving plans in windows. 3.3 GHz is probably optimal clock for P1 State because with higher clocks power efficiency rapidly deteriorates. Edited by noneis - 11 Jun 2017 at 11:53pm |
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Denroth
Newbie Joined: 02 Apr 2017 Status: Offline Points: 46 |
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Man, my ram back to 2933mhz T_T Intel burn test is instable with either 3066mhz or 3200mhz .. I tried with 1.5vdram 1.18vsoc timings 16-16-16-36 but it is unstable unfortunately :( |
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wardog
Moderator Group Joined: 15 Jul 2015 Status: Offline Points: 6447 |
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As I'm aware, there's no need to alter P1 and P2. Only P0. P1 and P2 are very technical and can create instability if not done properly/correctly. Plus I've read they(P1, P2) can hinder other settings, only aggravating stability. Those/These are my understandings. Just sayin' . |
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noneis
Newbie Joined: 07 Jun 2017 Status: Offline Points: 13 |
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You are overclocking only P-State 0. That works for me too. I was talking about P-State 1 and P-state 2. That works in pervious BIOS but not in new BIOS with AGESA 1.0.0.6. |
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datonyb
Senior Member Joined: 11 Apr 2017 Location: London U.K. Status: Offline Points: 3139 |
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in p states section i set a 3.9 cpu and a 1.306 voltage on first one and leave all others auto so pstates is 9c/9/27 i turn off cool n quiet, c6 etc then on advanced tab i set cpu fixed volts but leave voltage on auto there and llc level 2 when using monitoring software in windows is is very ridgidly fixed at 1.3 volts |
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3800X, powercolor reddevil vega64, gskill tridentz3866, taichix370, evga750watt gold |
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Lisanderus
Newbie Joined: 30 Apr 2017 Status: Offline Points: 10 |
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It's just a rough draft, I did not exactly set timings ... just dropped the main ones. Thanks for the advice, I'll try. The very fact - it's very difficult to pass POST at 3600. And the guy ran 3600 CL15 stable (i hope) - impressive. On the prev. bios (2.0) I had the best 12-12-12-26-CR1 at 3200mhz or something like that.
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noneis
Newbie Joined: 07 Jun 2017 Status: Offline Points: 13 |
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Your tRC is set at teoretical limit tRC = tRAS+tRP, try to set it higher. Stilt (B-Die) is using 54 for tRP=14 tRAS=28 that's 12T/29% above teoretical limit. My hynix kit at 2933 data rate requires 9T/20% above limit. So with Stilts ratio and your tRP,tRAS try something between 74 and 80+
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Lisanderus
Newbie Joined: 30 Apr 2017 Status: Offline Points: 10 |
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One question, how? Can you also show screenshot from RTC? My result is extremely unstable (1.4/1.25/2T). |
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